SigRAD - DPDK High Capacity Radar Solution

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• Overview
• SigRAD Functions
• Software Architecture

Overview

SigRAD is a DPDK enabled high capacity solution for signal processing and radar applications. SigRAD software allows customers to turn industry standard servers into high capacity radar processing, providing FFT, matched filtering, and other signal procesing functions. 32-core and 64-core CIM PCIe accelerator cards leverage Intel's DPDK to provide high-throughput, low-latency access to data plane x86 cores.

CIM® accelerator cards are thin, light weight, and have low power consumption. For example, three (3) 32-core cards can be inserted on a single riser in a 2U industry standard server and not exceed the riser power consumption limit of 150 W. A 1U server can be configured for as many as 256 CIM accelerator cores, and a 2U server for as many as 384 cores.

CIM® accelerator cards contain direct 1 GbE to 10 GbE network connections for high throughput and low latency radar processing, including virtualized systems.

CIM technology targets HPC applications in general, providing a low SWaP (size, weight, and power consumption) alternative to GPUs. SigRAD is a signal processing focused subset of the HPC applications supported by CIM.

HP DL380p 2U server with CIM accelerator installed. Up to six (6) accelerators can be installed in a 2U server with DPDK interface

CIM accelerator installed on middle riser and interfaced to eight (8) data plane x86 cores

SigRAD Functions

Below is a list of signal processing functions:

FFT

• up to 1M pt complex FFT

Matched Filtering

• Cross correlation

Convolution

Software Architecture

The block diagram below shows a high-throughput, low latency "data plane path" (blue line) between x86 cores and data plane signal processing cores. In this case, if the machine is virtualized, data plane processing -- including Ethernet I/O on the accelerator cards -- would not be visible to the VM. In this example, control plane processing is handled by x86 cores running Linux, and control plane related coordination follows the "control plane path" (red line).

DPDK + Accelerator Software Architecture